The present invention generally relates to data processing systems and more particularly to a control store addressing apparatus associated therewith.
It has become common place in the computer industry to develop data processors which include control stores which include a plurality of control or firmware words which are utilized to control the operation of such processors. These control stores are addressed based upon the contents of such control store words as well as other inputs depending upon the operation being executed in such data processor. In such next address generation logic it is important that the status of more than one test condition be simultaneously utilized to address the control store. If this were not provided, it would require loading of each one of these status or test conditions into, for example, a register on a clocked cycle basis. This would have to be done each time these test conditions change. It is accordingly desirable to test more than one such function, up to four such functions for example, simultaneously without having to load them into a clocked register. By providing such capability, the addressing of such control store is faster, and, accordingly, the overall performance of the data processor is increased.
It is accordingly a primary object of the present invention to provide an improved control store addressing mechanism for use in a data processing system.